/**
 * \file IfxEmem_mpu_bf.h
 * \brief
 * \copyright Copyright (c) 2018 Infineon Technologies AG. All rights reserved.
 *
 *
 * Version: TC39XB_UM_V1.0.0.R0
 * Specification: TC3xx User Manual V1.0.0
 * MAY BE CHANGED BY USER [yes/no]: No
 *
 *                                 IMPORTANT NOTICE
 *
 *
 * Infineon Technologies AG (Infineon) is supplying this file for use
 * exclusively with Infineon's microcontroller products. This file can be freely
 * distributed within development tools that are supporting such microcontroller
 * products.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
 * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 *
 * \defgroup IfxSfr_Emem_mpu_Registers_BitfieldsMask Bitfields mask and offset
 * \ingroup IfxSfr_Emem_mpu_Registers
 * 
 */
#ifndef IFXEMEM_MPU_BF_H
#define IFXEMEM_MPU_BF_H 1

/******************************************************************************/

/******************************************************************************/

/** \addtogroup IfxSfr_Emem_mpu_Registers_BitfieldsMask
 * \{  */
/** \brief Length for Ifx_EMEM_MPU_CLC_Bits.DISR */
#define IFX_EMEM_MPU_CLC_DISR_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_CLC_Bits.DISR */
#define IFX_EMEM_MPU_CLC_DISR_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_CLC_Bits.DISR */
#define IFX_EMEM_MPU_CLC_DISR_OFF (0u)

/** \brief Length for Ifx_EMEM_MPU_CLC_Bits.DISS */
#define IFX_EMEM_MPU_CLC_DISS_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_CLC_Bits.DISS */
#define IFX_EMEM_MPU_CLC_DISS_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_CLC_Bits.DISS */
#define IFX_EMEM_MPU_CLC_DISS_OFF (1u)

/** \brief Length for Ifx_EMEM_MPU_MODID_Bits.MOD_REV */
#define IFX_EMEM_MPU_MODID_MOD_REV_LEN (8u)

/** \brief Mask for Ifx_EMEM_MPU_MODID_Bits.MOD_REV */
#define IFX_EMEM_MPU_MODID_MOD_REV_MSK (0xffu)

/** \brief Offset for Ifx_EMEM_MPU_MODID_Bits.MOD_REV */
#define IFX_EMEM_MPU_MODID_MOD_REV_OFF (0u)

/** \brief Length for Ifx_EMEM_MPU_MODID_Bits.MOD_TYPE */
#define IFX_EMEM_MPU_MODID_MOD_TYPE_LEN (8u)

/** \brief Mask for Ifx_EMEM_MPU_MODID_Bits.MOD_TYPE */
#define IFX_EMEM_MPU_MODID_MOD_TYPE_MSK (0xffu)

/** \brief Offset for Ifx_EMEM_MPU_MODID_Bits.MOD_TYPE */
#define IFX_EMEM_MPU_MODID_MOD_TYPE_OFF (8u)

/** \brief Length for Ifx_EMEM_MPU_MODID_Bits.MOD_NUMBER */
#define IFX_EMEM_MPU_MODID_MOD_NUMBER_LEN (16u)

/** \brief Mask for Ifx_EMEM_MPU_MODID_Bits.MOD_NUMBER */
#define IFX_EMEM_MPU_MODID_MOD_NUMBER_MSK (0xffffu)

/** \brief Offset for Ifx_EMEM_MPU_MODID_Bits.MOD_NUMBER */
#define IFX_EMEM_MPU_MODID_MOD_NUMBER_OFF (16u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN0_Bits.EN0 */
#define IFX_EMEM_MPU_ACCEN0_EN0_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN0_Bits.EN0 */
#define IFX_EMEM_MPU_ACCEN0_EN0_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN0_Bits.EN0 */
#define IFX_EMEM_MPU_ACCEN0_EN0_OFF (0u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN0_Bits.EN1 */
#define IFX_EMEM_MPU_ACCEN0_EN1_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN0_Bits.EN1 */
#define IFX_EMEM_MPU_ACCEN0_EN1_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN0_Bits.EN1 */
#define IFX_EMEM_MPU_ACCEN0_EN1_OFF (1u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN0_Bits.EN2 */
#define IFX_EMEM_MPU_ACCEN0_EN2_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN0_Bits.EN2 */
#define IFX_EMEM_MPU_ACCEN0_EN2_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN0_Bits.EN2 */
#define IFX_EMEM_MPU_ACCEN0_EN2_OFF (2u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN0_Bits.EN3 */
#define IFX_EMEM_MPU_ACCEN0_EN3_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN0_Bits.EN3 */
#define IFX_EMEM_MPU_ACCEN0_EN3_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN0_Bits.EN3 */
#define IFX_EMEM_MPU_ACCEN0_EN3_OFF (3u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN0_Bits.EN4 */
#define IFX_EMEM_MPU_ACCEN0_EN4_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN0_Bits.EN4 */
#define IFX_EMEM_MPU_ACCEN0_EN4_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN0_Bits.EN4 */
#define IFX_EMEM_MPU_ACCEN0_EN4_OFF (4u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN0_Bits.EN5 */
#define IFX_EMEM_MPU_ACCEN0_EN5_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN0_Bits.EN5 */
#define IFX_EMEM_MPU_ACCEN0_EN5_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN0_Bits.EN5 */
#define IFX_EMEM_MPU_ACCEN0_EN5_OFF (5u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN0_Bits.EN6 */
#define IFX_EMEM_MPU_ACCEN0_EN6_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN0_Bits.EN6 */
#define IFX_EMEM_MPU_ACCEN0_EN6_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN0_Bits.EN6 */
#define IFX_EMEM_MPU_ACCEN0_EN6_OFF (6u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN0_Bits.EN7 */
#define IFX_EMEM_MPU_ACCEN0_EN7_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN0_Bits.EN7 */
#define IFX_EMEM_MPU_ACCEN0_EN7_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN0_Bits.EN7 */
#define IFX_EMEM_MPU_ACCEN0_EN7_OFF (7u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN0_Bits.EN8 */
#define IFX_EMEM_MPU_ACCEN0_EN8_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN0_Bits.EN8 */
#define IFX_EMEM_MPU_ACCEN0_EN8_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN0_Bits.EN8 */
#define IFX_EMEM_MPU_ACCEN0_EN8_OFF (8u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN0_Bits.EN9 */
#define IFX_EMEM_MPU_ACCEN0_EN9_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN0_Bits.EN9 */
#define IFX_EMEM_MPU_ACCEN0_EN9_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN0_Bits.EN9 */
#define IFX_EMEM_MPU_ACCEN0_EN9_OFF (9u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN0_Bits.EN10 */
#define IFX_EMEM_MPU_ACCEN0_EN10_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN0_Bits.EN10 */
#define IFX_EMEM_MPU_ACCEN0_EN10_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN0_Bits.EN10 */
#define IFX_EMEM_MPU_ACCEN0_EN10_OFF (10u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN0_Bits.EN11 */
#define IFX_EMEM_MPU_ACCEN0_EN11_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN0_Bits.EN11 */
#define IFX_EMEM_MPU_ACCEN0_EN11_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN0_Bits.EN11 */
#define IFX_EMEM_MPU_ACCEN0_EN11_OFF (11u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN0_Bits.EN12 */
#define IFX_EMEM_MPU_ACCEN0_EN12_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN0_Bits.EN12 */
#define IFX_EMEM_MPU_ACCEN0_EN12_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN0_Bits.EN12 */
#define IFX_EMEM_MPU_ACCEN0_EN12_OFF (12u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN0_Bits.EN13 */
#define IFX_EMEM_MPU_ACCEN0_EN13_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN0_Bits.EN13 */
#define IFX_EMEM_MPU_ACCEN0_EN13_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN0_Bits.EN13 */
#define IFX_EMEM_MPU_ACCEN0_EN13_OFF (13u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN0_Bits.EN14 */
#define IFX_EMEM_MPU_ACCEN0_EN14_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN0_Bits.EN14 */
#define IFX_EMEM_MPU_ACCEN0_EN14_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN0_Bits.EN14 */
#define IFX_EMEM_MPU_ACCEN0_EN14_OFF (14u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN0_Bits.EN15 */
#define IFX_EMEM_MPU_ACCEN0_EN15_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN0_Bits.EN15 */
#define IFX_EMEM_MPU_ACCEN0_EN15_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN0_Bits.EN15 */
#define IFX_EMEM_MPU_ACCEN0_EN15_OFF (15u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN0_Bits.EN16 */
#define IFX_EMEM_MPU_ACCEN0_EN16_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN0_Bits.EN16 */
#define IFX_EMEM_MPU_ACCEN0_EN16_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN0_Bits.EN16 */
#define IFX_EMEM_MPU_ACCEN0_EN16_OFF (16u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN0_Bits.EN17 */
#define IFX_EMEM_MPU_ACCEN0_EN17_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN0_Bits.EN17 */
#define IFX_EMEM_MPU_ACCEN0_EN17_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN0_Bits.EN17 */
#define IFX_EMEM_MPU_ACCEN0_EN17_OFF (17u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN0_Bits.EN18 */
#define IFX_EMEM_MPU_ACCEN0_EN18_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN0_Bits.EN18 */
#define IFX_EMEM_MPU_ACCEN0_EN18_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN0_Bits.EN18 */
#define IFX_EMEM_MPU_ACCEN0_EN18_OFF (18u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN0_Bits.EN19 */
#define IFX_EMEM_MPU_ACCEN0_EN19_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN0_Bits.EN19 */
#define IFX_EMEM_MPU_ACCEN0_EN19_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN0_Bits.EN19 */
#define IFX_EMEM_MPU_ACCEN0_EN19_OFF (19u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN0_Bits.EN20 */
#define IFX_EMEM_MPU_ACCEN0_EN20_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN0_Bits.EN20 */
#define IFX_EMEM_MPU_ACCEN0_EN20_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN0_Bits.EN20 */
#define IFX_EMEM_MPU_ACCEN0_EN20_OFF (20u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN0_Bits.EN21 */
#define IFX_EMEM_MPU_ACCEN0_EN21_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN0_Bits.EN21 */
#define IFX_EMEM_MPU_ACCEN0_EN21_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN0_Bits.EN21 */
#define IFX_EMEM_MPU_ACCEN0_EN21_OFF (21u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN0_Bits.EN22 */
#define IFX_EMEM_MPU_ACCEN0_EN22_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN0_Bits.EN22 */
#define IFX_EMEM_MPU_ACCEN0_EN22_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN0_Bits.EN22 */
#define IFX_EMEM_MPU_ACCEN0_EN22_OFF (22u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN0_Bits.EN23 */
#define IFX_EMEM_MPU_ACCEN0_EN23_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN0_Bits.EN23 */
#define IFX_EMEM_MPU_ACCEN0_EN23_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN0_Bits.EN23 */
#define IFX_EMEM_MPU_ACCEN0_EN23_OFF (23u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN0_Bits.EN24 */
#define IFX_EMEM_MPU_ACCEN0_EN24_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN0_Bits.EN24 */
#define IFX_EMEM_MPU_ACCEN0_EN24_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN0_Bits.EN24 */
#define IFX_EMEM_MPU_ACCEN0_EN24_OFF (24u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN0_Bits.EN25 */
#define IFX_EMEM_MPU_ACCEN0_EN25_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN0_Bits.EN25 */
#define IFX_EMEM_MPU_ACCEN0_EN25_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN0_Bits.EN25 */
#define IFX_EMEM_MPU_ACCEN0_EN25_OFF (25u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN0_Bits.EN26 */
#define IFX_EMEM_MPU_ACCEN0_EN26_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN0_Bits.EN26 */
#define IFX_EMEM_MPU_ACCEN0_EN26_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN0_Bits.EN26 */
#define IFX_EMEM_MPU_ACCEN0_EN26_OFF (26u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN0_Bits.EN27 */
#define IFX_EMEM_MPU_ACCEN0_EN27_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN0_Bits.EN27 */
#define IFX_EMEM_MPU_ACCEN0_EN27_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN0_Bits.EN27 */
#define IFX_EMEM_MPU_ACCEN0_EN27_OFF (27u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN0_Bits.EN28 */
#define IFX_EMEM_MPU_ACCEN0_EN28_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN0_Bits.EN28 */
#define IFX_EMEM_MPU_ACCEN0_EN28_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN0_Bits.EN28 */
#define IFX_EMEM_MPU_ACCEN0_EN28_OFF (28u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN0_Bits.EN29 */
#define IFX_EMEM_MPU_ACCEN0_EN29_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN0_Bits.EN29 */
#define IFX_EMEM_MPU_ACCEN0_EN29_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN0_Bits.EN29 */
#define IFX_EMEM_MPU_ACCEN0_EN29_OFF (29u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN0_Bits.EN30 */
#define IFX_EMEM_MPU_ACCEN0_EN30_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN0_Bits.EN30 */
#define IFX_EMEM_MPU_ACCEN0_EN30_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN0_Bits.EN30 */
#define IFX_EMEM_MPU_ACCEN0_EN30_OFF (30u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN0_Bits.EN31 */
#define IFX_EMEM_MPU_ACCEN0_EN31_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN0_Bits.EN31 */
#define IFX_EMEM_MPU_ACCEN0_EN31_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN0_Bits.EN31 */
#define IFX_EMEM_MPU_ACCEN0_EN31_OFF (31u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN1_Bits.EN32 */
#define IFX_EMEM_MPU_ACCEN1_EN32_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN1_Bits.EN32 */
#define IFX_EMEM_MPU_ACCEN1_EN32_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN1_Bits.EN32 */
#define IFX_EMEM_MPU_ACCEN1_EN32_OFF (0u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN1_Bits.EN33 */
#define IFX_EMEM_MPU_ACCEN1_EN33_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN1_Bits.EN33 */
#define IFX_EMEM_MPU_ACCEN1_EN33_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN1_Bits.EN33 */
#define IFX_EMEM_MPU_ACCEN1_EN33_OFF (1u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN1_Bits.EN34 */
#define IFX_EMEM_MPU_ACCEN1_EN34_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN1_Bits.EN34 */
#define IFX_EMEM_MPU_ACCEN1_EN34_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN1_Bits.EN34 */
#define IFX_EMEM_MPU_ACCEN1_EN34_OFF (2u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN1_Bits.EN35 */
#define IFX_EMEM_MPU_ACCEN1_EN35_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN1_Bits.EN35 */
#define IFX_EMEM_MPU_ACCEN1_EN35_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN1_Bits.EN35 */
#define IFX_EMEM_MPU_ACCEN1_EN35_OFF (3u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN1_Bits.EN36 */
#define IFX_EMEM_MPU_ACCEN1_EN36_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN1_Bits.EN36 */
#define IFX_EMEM_MPU_ACCEN1_EN36_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN1_Bits.EN36 */
#define IFX_EMEM_MPU_ACCEN1_EN36_OFF (4u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN1_Bits.EN37 */
#define IFX_EMEM_MPU_ACCEN1_EN37_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN1_Bits.EN37 */
#define IFX_EMEM_MPU_ACCEN1_EN37_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN1_Bits.EN37 */
#define IFX_EMEM_MPU_ACCEN1_EN37_OFF (5u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN1_Bits.EN38 */
#define IFX_EMEM_MPU_ACCEN1_EN38_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN1_Bits.EN38 */
#define IFX_EMEM_MPU_ACCEN1_EN38_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN1_Bits.EN38 */
#define IFX_EMEM_MPU_ACCEN1_EN38_OFF (6u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN1_Bits.EN39 */
#define IFX_EMEM_MPU_ACCEN1_EN39_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN1_Bits.EN39 */
#define IFX_EMEM_MPU_ACCEN1_EN39_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN1_Bits.EN39 */
#define IFX_EMEM_MPU_ACCEN1_EN39_OFF (7u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN1_Bits.EN40 */
#define IFX_EMEM_MPU_ACCEN1_EN40_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN1_Bits.EN40 */
#define IFX_EMEM_MPU_ACCEN1_EN40_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN1_Bits.EN40 */
#define IFX_EMEM_MPU_ACCEN1_EN40_OFF (8u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN1_Bits.EN41 */
#define IFX_EMEM_MPU_ACCEN1_EN41_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN1_Bits.EN41 */
#define IFX_EMEM_MPU_ACCEN1_EN41_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN1_Bits.EN41 */
#define IFX_EMEM_MPU_ACCEN1_EN41_OFF (9u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN1_Bits.EN42 */
#define IFX_EMEM_MPU_ACCEN1_EN42_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN1_Bits.EN42 */
#define IFX_EMEM_MPU_ACCEN1_EN42_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN1_Bits.EN42 */
#define IFX_EMEM_MPU_ACCEN1_EN42_OFF (10u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN1_Bits.EN43 */
#define IFX_EMEM_MPU_ACCEN1_EN43_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN1_Bits.EN43 */
#define IFX_EMEM_MPU_ACCEN1_EN43_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN1_Bits.EN43 */
#define IFX_EMEM_MPU_ACCEN1_EN43_OFF (11u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN1_Bits.EN44 */
#define IFX_EMEM_MPU_ACCEN1_EN44_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN1_Bits.EN44 */
#define IFX_EMEM_MPU_ACCEN1_EN44_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN1_Bits.EN44 */
#define IFX_EMEM_MPU_ACCEN1_EN44_OFF (12u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN1_Bits.EN45 */
#define IFX_EMEM_MPU_ACCEN1_EN45_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN1_Bits.EN45 */
#define IFX_EMEM_MPU_ACCEN1_EN45_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN1_Bits.EN45 */
#define IFX_EMEM_MPU_ACCEN1_EN45_OFF (13u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN1_Bits.EN46 */
#define IFX_EMEM_MPU_ACCEN1_EN46_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN1_Bits.EN46 */
#define IFX_EMEM_MPU_ACCEN1_EN46_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN1_Bits.EN46 */
#define IFX_EMEM_MPU_ACCEN1_EN46_OFF (14u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN1_Bits.EN47 */
#define IFX_EMEM_MPU_ACCEN1_EN47_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN1_Bits.EN47 */
#define IFX_EMEM_MPU_ACCEN1_EN47_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN1_Bits.EN47 */
#define IFX_EMEM_MPU_ACCEN1_EN47_OFF (15u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN1_Bits.EN48 */
#define IFX_EMEM_MPU_ACCEN1_EN48_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN1_Bits.EN48 */
#define IFX_EMEM_MPU_ACCEN1_EN48_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN1_Bits.EN48 */
#define IFX_EMEM_MPU_ACCEN1_EN48_OFF (16u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN1_Bits.EN49 */
#define IFX_EMEM_MPU_ACCEN1_EN49_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN1_Bits.EN49 */
#define IFX_EMEM_MPU_ACCEN1_EN49_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN1_Bits.EN49 */
#define IFX_EMEM_MPU_ACCEN1_EN49_OFF (17u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN1_Bits.EN50 */
#define IFX_EMEM_MPU_ACCEN1_EN50_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN1_Bits.EN50 */
#define IFX_EMEM_MPU_ACCEN1_EN50_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN1_Bits.EN50 */
#define IFX_EMEM_MPU_ACCEN1_EN50_OFF (18u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN1_Bits.EN51 */
#define IFX_EMEM_MPU_ACCEN1_EN51_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN1_Bits.EN51 */
#define IFX_EMEM_MPU_ACCEN1_EN51_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN1_Bits.EN51 */
#define IFX_EMEM_MPU_ACCEN1_EN51_OFF (19u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN1_Bits.EN52 */
#define IFX_EMEM_MPU_ACCEN1_EN52_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN1_Bits.EN52 */
#define IFX_EMEM_MPU_ACCEN1_EN52_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN1_Bits.EN52 */
#define IFX_EMEM_MPU_ACCEN1_EN52_OFF (20u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN1_Bits.EN53 */
#define IFX_EMEM_MPU_ACCEN1_EN53_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN1_Bits.EN53 */
#define IFX_EMEM_MPU_ACCEN1_EN53_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN1_Bits.EN53 */
#define IFX_EMEM_MPU_ACCEN1_EN53_OFF (21u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN1_Bits.EN54 */
#define IFX_EMEM_MPU_ACCEN1_EN54_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN1_Bits.EN54 */
#define IFX_EMEM_MPU_ACCEN1_EN54_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN1_Bits.EN54 */
#define IFX_EMEM_MPU_ACCEN1_EN54_OFF (22u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN1_Bits.EN55 */
#define IFX_EMEM_MPU_ACCEN1_EN55_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN1_Bits.EN55 */
#define IFX_EMEM_MPU_ACCEN1_EN55_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN1_Bits.EN55 */
#define IFX_EMEM_MPU_ACCEN1_EN55_OFF (23u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN1_Bits.EN56 */
#define IFX_EMEM_MPU_ACCEN1_EN56_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN1_Bits.EN56 */
#define IFX_EMEM_MPU_ACCEN1_EN56_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN1_Bits.EN56 */
#define IFX_EMEM_MPU_ACCEN1_EN56_OFF (24u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN1_Bits.EN57 */
#define IFX_EMEM_MPU_ACCEN1_EN57_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN1_Bits.EN57 */
#define IFX_EMEM_MPU_ACCEN1_EN57_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN1_Bits.EN57 */
#define IFX_EMEM_MPU_ACCEN1_EN57_OFF (25u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN1_Bits.EN58 */
#define IFX_EMEM_MPU_ACCEN1_EN58_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN1_Bits.EN58 */
#define IFX_EMEM_MPU_ACCEN1_EN58_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN1_Bits.EN58 */
#define IFX_EMEM_MPU_ACCEN1_EN58_OFF (26u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN1_Bits.EN59 */
#define IFX_EMEM_MPU_ACCEN1_EN59_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN1_Bits.EN59 */
#define IFX_EMEM_MPU_ACCEN1_EN59_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN1_Bits.EN59 */
#define IFX_EMEM_MPU_ACCEN1_EN59_OFF (27u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN1_Bits.EN60 */
#define IFX_EMEM_MPU_ACCEN1_EN60_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN1_Bits.EN60 */
#define IFX_EMEM_MPU_ACCEN1_EN60_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN1_Bits.EN60 */
#define IFX_EMEM_MPU_ACCEN1_EN60_OFF (28u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN1_Bits.EN61 */
#define IFX_EMEM_MPU_ACCEN1_EN61_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN1_Bits.EN61 */
#define IFX_EMEM_MPU_ACCEN1_EN61_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN1_Bits.EN61 */
#define IFX_EMEM_MPU_ACCEN1_EN61_OFF (29u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN1_Bits.EN62 */
#define IFX_EMEM_MPU_ACCEN1_EN62_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN1_Bits.EN62 */
#define IFX_EMEM_MPU_ACCEN1_EN62_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN1_Bits.EN62 */
#define IFX_EMEM_MPU_ACCEN1_EN62_OFF (30u)

/** \brief Length for Ifx_EMEM_MPU_ACCEN1_Bits.EN63 */
#define IFX_EMEM_MPU_ACCEN1_EN63_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_ACCEN1_Bits.EN63 */
#define IFX_EMEM_MPU_ACCEN1_EN63_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_ACCEN1_Bits.EN63 */
#define IFX_EMEM_MPU_ACCEN1_EN63_OFF (31u)

/** \brief Length for Ifx_EMEM_MPU_MEMCON_Bits.INTERR */
#define IFX_EMEM_MPU_MEMCON_INTERR_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_MEMCON_Bits.INTERR */
#define IFX_EMEM_MPU_MEMCON_INTERR_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_MEMCON_Bits.INTERR */
#define IFX_EMEM_MPU_MEMCON_INTERR_OFF (2u)

/** \brief Length for Ifx_EMEM_MPU_MEMCON_Bits.RMWERR */
#define IFX_EMEM_MPU_MEMCON_RMWERR_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_MEMCON_Bits.RMWERR */
#define IFX_EMEM_MPU_MEMCON_RMWERR_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_MEMCON_Bits.RMWERR */
#define IFX_EMEM_MPU_MEMCON_RMWERR_OFF (4u)

/** \brief Length for Ifx_EMEM_MPU_MEMCON_Bits.DATAERR */
#define IFX_EMEM_MPU_MEMCON_DATAERR_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_MEMCON_Bits.DATAERR */
#define IFX_EMEM_MPU_MEMCON_DATAERR_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_MEMCON_Bits.DATAERR */
#define IFX_EMEM_MPU_MEMCON_DATAERR_OFF (6u)

/** \brief Length for Ifx_EMEM_MPU_MEMCON_Bits.ADDERR */
#define IFX_EMEM_MPU_MEMCON_ADDERR_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_MEMCON_Bits.ADDERR */
#define IFX_EMEM_MPU_MEMCON_ADDERR_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_MEMCON_Bits.ADDERR */
#define IFX_EMEM_MPU_MEMCON_ADDERR_OFF (7u)

/** \brief Length for Ifx_EMEM_MPU_MEMCON_Bits.PMIC */
#define IFX_EMEM_MPU_MEMCON_PMIC_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_MEMCON_Bits.PMIC */
#define IFX_EMEM_MPU_MEMCON_PMIC_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_MEMCON_Bits.PMIC */
#define IFX_EMEM_MPU_MEMCON_PMIC_OFF (8u)

/** \brief Length for Ifx_EMEM_MPU_MEMCON_Bits.ERRDIS */
#define IFX_EMEM_MPU_MEMCON_ERRDIS_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_MEMCON_Bits.ERRDIS */
#define IFX_EMEM_MPU_MEMCON_ERRDIS_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_MEMCON_Bits.ERRDIS */
#define IFX_EMEM_MPU_MEMCON_ERRDIS_OFF (9u)

/** \brief Length for Ifx_EMEM_MPU_SCTRL_Bits.GED */
#define IFX_EMEM_MPU_SCTRL_GED_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_SCTRL_Bits.GED */
#define IFX_EMEM_MPU_SCTRL_GED_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_SCTRL_Bits.GED */
#define IFX_EMEM_MPU_SCTRL_GED_OFF (0u)

/** \brief Length for Ifx_EMEM_MPU_SCTRL_Bits.GEC */
#define IFX_EMEM_MPU_SCTRL_GEC_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_SCTRL_Bits.GEC */
#define IFX_EMEM_MPU_SCTRL_GEC_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_SCTRL_Bits.GEC */
#define IFX_EMEM_MPU_SCTRL_GEC_OFF (1u)

/** \brief Length for Ifx_EMEM_MPU_SCTRL_Bits.LSEN */
#define IFX_EMEM_MPU_SCTRL_LSEN_LEN (2u)

/** \brief Mask for Ifx_EMEM_MPU_SCTRL_Bits.LSEN */
#define IFX_EMEM_MPU_SCTRL_LSEN_MSK (0x3u)

/** \brief Offset for Ifx_EMEM_MPU_SCTRL_Bits.LSEN */
#define IFX_EMEM_MPU_SCTRL_LSEN_OFF (8u)

/** \brief Length for Ifx_EMEM_MPU_SCTRL_Bits.LSTST */
#define IFX_EMEM_MPU_SCTRL_LSTST_LEN (2u)

/** \brief Mask for Ifx_EMEM_MPU_SCTRL_Bits.LSTST */
#define IFX_EMEM_MPU_SCTRL_LSTST_MSK (0x3u)

/** \brief Offset for Ifx_EMEM_MPU_SCTRL_Bits.LSTST */
#define IFX_EMEM_MPU_SCTRL_LSTST_OFF (10u)

/** \brief Length for Ifx_EMEM_MPU_SCTRL_Bits.LSSTAT */
#define IFX_EMEM_MPU_SCTRL_LSSTAT_LEN (2u)

/** \brief Mask for Ifx_EMEM_MPU_SCTRL_Bits.LSSTAT */
#define IFX_EMEM_MPU_SCTRL_LSSTAT_MSK (0x3u)

/** \brief Offset for Ifx_EMEM_MPU_SCTRL_Bits.LSSTAT */
#define IFX_EMEM_MPU_SCTRL_LSSTAT_OFF (16u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNLA_Bits.ADDR */
#define IFX_EMEM_MPU_RGNWRN_RGNLA_ADDR_LEN (27u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNLA_Bits.ADDR */
#define IFX_EMEM_MPU_RGNWRN_RGNLA_ADDR_MSK (0x7ffffffu)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNLA_Bits.ADDR */
#define IFX_EMEM_MPU_RGNWRN_RGNLA_ADDR_OFF (5u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNUA_Bits.ADDR */
#define IFX_EMEM_MPU_RGNWRN_RGNUA_ADDR_LEN (27u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNUA_Bits.ADDR */
#define IFX_EMEM_MPU_RGNWRN_RGNUA_ADDR_MSK (0x7ffffffu)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNUA_Bits.ADDR */
#define IFX_EMEM_MPU_RGNWRN_RGNUA_ADDR_OFF (5u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN0 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN0_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN0 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN0_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN0 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN0_OFF (0u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN1 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN1_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN1 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN1_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN1 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN1_OFF (1u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN2 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN2_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN2 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN2_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN2 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN2_OFF (2u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN3 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN3_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN3 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN3_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN3 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN3_OFF (3u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN4 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN4_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN4 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN4_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN4 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN4_OFF (4u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN5 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN5_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN5 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN5_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN5 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN5_OFF (5u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN6 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN6_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN6 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN6_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN6 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN6_OFF (6u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN7 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN7_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN7 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN7_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN7 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN7_OFF (7u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN8 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN8_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN8 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN8_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN8 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN8_OFF (8u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN9 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN9_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN9 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN9_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN9 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN9_OFF (9u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN10 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN10_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN10 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN10_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN10 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN10_OFF (10u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN11 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN11_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN11 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN11_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN11 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN11_OFF (11u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN12 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN12_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN12 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN12_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN12 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN12_OFF (12u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN13 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN13_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN13 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN13_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN13 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN13_OFF (13u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN14 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN14_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN14 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN14_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN14 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN14_OFF (14u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN15 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN15_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN15 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN15_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN15 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN15_OFF (15u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN16 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN16_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN16 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN16_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN16 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN16_OFF (16u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN17 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN17_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN17 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN17_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN17 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN17_OFF (17u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN18 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN18_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN18 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN18_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN18 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN18_OFF (18u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN19 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN19_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN19 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN19_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN19 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN19_OFF (19u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN20 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN20_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN20 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN20_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN20 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN20_OFF (20u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN21 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN21_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN21 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN21_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN21 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN21_OFF (21u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN22 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN22_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN22 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN22_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN22 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN22_OFF (22u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN23 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN23_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN23 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN23_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN23 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN23_OFF (23u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN24 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN24_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN24 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN24_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN24 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN24_OFF (24u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN25 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN25_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN25 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN25_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN25 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN25_OFF (25u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN26 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN26_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN26 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN26_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN26 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN26_OFF (26u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN27 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN27_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN27 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN27_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN27 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN27_OFF (27u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN28 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN28_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN28 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN28_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN28 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN28_OFF (28u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN29 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN29_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN29 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN29_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN29 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN29_OFF (29u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN30 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN30_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN30 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN30_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN30 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN30_OFF (30u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN31 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN31_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN31 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN31_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWA_Bits.EN31 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWA_EN31_OFF (31u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN32 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN32_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN32 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN32_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN32 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN32_OFF (0u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN33 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN33_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN33 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN33_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN33 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN33_OFF (1u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN34 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN34_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN34 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN34_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN34 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN34_OFF (2u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN35 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN35_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN35 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN35_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN35 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN35_OFF (3u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN36 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN36_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN36 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN36_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN36 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN36_OFF (4u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN37 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN37_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN37 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN37_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN37 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN37_OFF (5u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN38 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN38_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN38 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN38_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN38 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN38_OFF (6u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN39 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN39_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN39 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN39_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN39 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN39_OFF (7u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN40 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN40_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN40 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN40_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN40 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN40_OFF (8u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN41 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN41_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN41 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN41_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN41 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN41_OFF (9u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN42 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN42_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN42 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN42_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN42 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN42_OFF (10u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN43 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN43_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN43 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN43_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN43 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN43_OFF (11u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN44 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN44_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN44 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN44_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN44 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN44_OFF (12u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN45 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN45_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN45 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN45_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN45 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN45_OFF (13u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN46 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN46_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN46 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN46_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN46 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN46_OFF (14u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN47 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN47_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN47 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN47_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN47 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN47_OFF (15u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN48 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN48_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN48 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN48_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN48 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN48_OFF (16u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN49 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN49_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN49 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN49_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN49 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN49_OFF (17u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN50 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN50_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN50 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN50_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN50 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN50_OFF (18u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN51 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN51_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN51 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN51_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN51 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN51_OFF (19u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN52 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN52_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN52 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN52_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN52 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN52_OFF (20u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN53 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN53_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN53 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN53_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN53 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN53_OFF (21u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN54 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN54_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN54 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN54_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN54 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN54_OFF (22u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN55 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN55_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN55 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN55_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN55 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN55_OFF (23u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN56 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN56_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN56 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN56_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN56 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN56_OFF (24u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN57 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN57_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN57 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN57_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN57 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN57_OFF (25u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN58 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN58_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN58 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN58_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN58 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN58_OFF (26u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN59 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN59_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN59 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN59_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN59 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN59_OFF (27u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN60 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN60_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN60 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN60_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN60 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN60_OFF (28u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN61 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN61_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN61 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN61_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN61 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN61_OFF (29u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN62 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN62_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN62 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN62_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN62 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN62_OFF (30u)

/** \brief Length for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN63 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN63_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN63 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN63_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNWRN_RGNACCENWB_Bits.EN63 */
#define IFX_EMEM_MPU_RGNWRN_RGNACCENWB_EN63_OFF (31u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN0 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN0_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN0 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN0_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN0 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN0_OFF (0u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN1 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN1_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN1 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN1_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN1 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN1_OFF (1u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN2 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN2_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN2 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN2_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN2 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN2_OFF (2u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN3 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN3_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN3 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN3_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN3 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN3_OFF (3u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN4 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN4_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN4 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN4_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN4 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN4_OFF (4u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN5 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN5_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN5 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN5_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN5 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN5_OFF (5u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN6 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN6_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN6 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN6_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN6 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN6_OFF (6u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN7 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN7_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN7 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN7_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN7 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN7_OFF (7u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN8 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN8_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN8 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN8_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN8 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN8_OFF (8u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN9 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN9_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN9 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN9_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN9 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN9_OFF (9u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN10 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN10_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN10 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN10_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN10 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN10_OFF (10u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN11 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN11_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN11 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN11_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN11 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN11_OFF (11u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN12 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN12_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN12 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN12_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN12 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN12_OFF (12u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN13 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN13_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN13 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN13_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN13 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN13_OFF (13u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN14 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN14_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN14 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN14_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN14 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN14_OFF (14u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN15 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN15_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN15 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN15_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN15 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN15_OFF (15u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN16 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN16_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN16 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN16_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN16 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN16_OFF (16u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN17 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN17_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN17 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN17_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN17 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN17_OFF (17u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN18 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN18_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN18 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN18_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN18 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN18_OFF (18u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN19 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN19_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN19 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN19_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN19 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN19_OFF (19u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN20 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN20_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN20 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN20_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN20 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN20_OFF (20u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN21 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN21_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN21 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN21_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN21 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN21_OFF (21u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN22 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN22_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN22 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN22_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN22 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN22_OFF (22u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN23 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN23_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN23 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN23_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN23 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN23_OFF (23u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN24 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN24_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN24 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN24_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN24 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN24_OFF (24u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN25 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN25_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN25 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN25_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN25 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN25_OFF (25u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN26 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN26_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN26 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN26_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN26 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN26_OFF (26u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN27 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN27_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN27 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN27_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN27 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN27_OFF (27u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN28 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN28_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN28 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN28_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN28 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN28_OFF (28u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN29 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN29_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN29 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN29_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN29 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN29_OFF (29u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN30 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN30_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN30 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN30_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN30 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN30_OFF (30u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN31 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN31_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN31 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN31_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRA_Bits.EN31 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRA_EN31_OFF (31u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN32 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN32_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN32 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN32_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN32 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN32_OFF (0u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN33 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN33_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN33 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN33_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN33 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN33_OFF (1u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN34 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN34_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN34 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN34_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN34 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN34_OFF (2u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN35 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN35_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN35 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN35_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN35 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN35_OFF (3u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN36 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN36_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN36 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN36_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN36 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN36_OFF (4u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN37 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN37_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN37 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN37_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN37 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN37_OFF (5u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN38 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN38_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN38 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN38_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN38 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN38_OFF (6u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN39 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN39_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN39 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN39_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN39 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN39_OFF (7u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN40 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN40_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN40 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN40_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN40 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN40_OFF (8u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN41 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN41_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN41 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN41_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN41 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN41_OFF (9u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN42 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN42_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN42 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN42_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN42 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN42_OFF (10u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN43 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN43_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN43 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN43_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN43 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN43_OFF (11u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN44 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN44_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN44 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN44_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN44 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN44_OFF (12u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN45 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN45_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN45 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN45_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN45 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN45_OFF (13u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN46 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN46_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN46 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN46_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN46 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN46_OFF (14u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN47 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN47_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN47 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN47_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN47 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN47_OFF (15u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN48 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN48_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN48 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN48_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN48 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN48_OFF (16u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN49 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN49_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN49 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN49_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN49 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN49_OFF (17u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN50 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN50_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN50 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN50_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN50 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN50_OFF (18u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN51 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN51_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN51 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN51_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN51 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN51_OFF (19u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN52 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN52_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN52 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN52_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN52 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN52_OFF (20u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN53 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN53_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN53 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN53_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN53 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN53_OFF (21u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN54 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN54_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN54 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN54_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN54 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN54_OFF (22u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN55 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN55_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN55 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN55_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN55 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN55_OFF (23u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN56 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN56_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN56 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN56_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN56 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN56_OFF (24u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN57 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN57_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN57 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN57_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN57 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN57_OFF (25u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN58 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN58_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN58 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN58_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN58 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN58_OFF (26u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN59 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN59_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN59 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN59_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN59 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN59_OFF (27u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN60 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN60_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN60 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN60_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN60 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN60_OFF (28u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN61 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN61_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN61 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN61_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN61 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN61_OFF (29u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN62 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN62_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN62 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN62_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN62 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN62_OFF (30u)

/** \brief Length for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN63 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN63_LEN (1u)

/** \brief Mask for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN63 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN63_MSK (0x1u)

/** \brief Offset for Ifx_EMEM_MPU_RGNACCEN_RGNACCENRB_Bits.EN63 */
#define IFX_EMEM_MPU_RGNACCEN_RGNACCENRB_EN63_OFF (31u)

/** \}  */

/******************************************************************************/

/******************************************************************************/

#endif /* IFXEMEM_MPU_BF_H */
